Abstract–We report on the performance of the MIMOSA8 chip. The chip is a 128 x 32 pixels array where 8 columns have analog direct outputs and 24 have discriminated outputs. The array is divided in four blocks of pixels with different conversion factors and is controlled by a serially programmable sequencer. MIMOSA8 is a representative of the CMOS sensors development option considered as a promising candidate for the Vertex detector of the future International Linear Collider (ILC). The readout technique, implemented on the chip, combines high spatial resolution capabilities with high processing readout speed. Data acquisition, providing control of the chip and signal buffering, linked to a VME system was made on the 8 analog outputs. Analog data, without and with a 55Fe X ray source, were acquired and processed using off-line analysis software. From the reconstruction of pixel clusters, built around a central pixel, the charge spread is limited to the closest 25 pixels and almost all the available charge is collected. The position of the total charge collection peak (and subsequently the charge-to-voltage conversion factor) stays unaffected when the clocking frequency is increased even up to 150 MHz (13.6 µs readout time per frame). The discriminators, placed in the readout chain, have proven fully functional. Beam tests have been made with high energy electrons at DESY (Germany) to study detection efficiency. |
